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ae3.0e fujitsu semiconductor data sheet 1 (9/2004) memory mobile fcram tm cmos 16m bit (1 m word x 16 bit) mobile phone application specific memory mb82ds01181e -70l-a cmos 1,048,576-word x 16 bit fast cycle random access memory with low power sram interface description the fujitsu mb82ds01181e is a cmos fast cycle random access memory (fcram) with asynchronous static random access memory (sram) interface containing 16,777,216 storages accessible in a 16-bit format. this mb82ds01181e is suited for mobile applications such as cellular handset and pda. features notice: fcram is a trademark of fujitsu limited, japan ? asynchronous sram interface fast random access time t ce = 70ns (-70) low voltage operating condition v dd = +1.7v to +1.95v wide operating temperature t a = -30c to +85c byte control by lb and ub low power consumption i dda1 = 20ma max i dds1 = 100 a max power down mode
2 (ae3.0e) mb82ds01181e -70l-a pin description block diagram pin name description a 19 to a 0 address input ce 1 chip enable (low active) ce2 chip enable (high active) we write enable (low active) oe output enable (low active) ub upper byte control (low active) lb lower byte control (low active) dq 16 - 9 upper byte data input/output dq 8 - 1 lower byte data input/output v dd power supply v ss ground a19 to a0 address latch & buffer row decoder memory cell array 16,777,216bit column / decoder input data latch & control output data control dq16 to dq9 dq8 to dq1 address latch & buffer sense / switch v dd v ss we lb ce2 ub timing control input / output buffer ce 1 power control oe
3 (ae3.0e) mb82ds01181e -70l-a function truth table notes l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance *1: should not be kept this logic condition longer than 1 s. please contact local fujitsu representative for the relaxation of 1 s limitation. *2: power down mode can be entered from standby state and all dq pins are in high-z state. *3: can be either v il or v ih but must be valid before read or write. mode note ce2 ce 1we oe lb ub a19-0 dq8-1 dq16-9 i dd data retention standby (deselect) hhxxxx x high-zhigh-zi dds yes output disable *1 hl h h x x *3 high-z high-z i dda output disable (no read) hl h h valid high-z high-z read (upper byte) h l valid high-z output valid read (lower byte) l h valid output valid high-z read (word) l l valid output valid output valid no write l h h h valid invalid invalid write (upper byte) h l valid invalid input valid write (lower byte) l h valid input valid invalid write (word) l l valid input valid input valid power down *2lxxxxx x high-zhigh-zi ddp no
4 (ae3.0e) mb82ds01181e -70l-a absolute maximum ratings (see warning below.) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions (see warning below.) (referenced to v ss ) notes *1: maximum dc voltage on input and i/o pins are v dd +0.2v. during voltage transitions, inputs may positive overshoot to v dd +1.0v for periods of up to 5 ns. *2: minimum dc voltage on input or i/o pins are -0.3v. during voltage transitions, inputs may negative overshoot v ss to -1.0v for periods of up to 5ns. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the device?s electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. package pin capacitance test conditions: t a = 25c, f = 1.0 mhz parameter symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage at any pin relative to v ss v in , v out -0.5 to +3.6 v short circuit output current i out + 50 ma storage temperature t stg -55 to +125 o c parameter notes symbol min. max. unit supply voltage v dd 1.7 1.95 v v ss 00v high level input voltage *1 v ih v dd *0.8 v dd +0.2 v low level input voltage *2 v il -0.3 v dd *0.2 v ambient temperature t a -30 85 c symbol description test setup typ. max. unit c in1 address input capacitance v in = 0v ? 5 pf c in2 control input capacitance v in = 0v ? 5 pf c io data input/output capacitance v io = 0v ? 8 pf
5 (ae3.0e) mb82ds01181e -70l-a dc characteristics (under recommended operating conditions unless otherwise noted) note *1,*2,*3 notes *1: all voltages are referenced to vss. *2: dc characteristics are measured after following power-up timing. *3: i out depends on the output load conditions. parameter symbol test conditions min. max. unit input leakage current i li v in = v ss to v dd -1.0 +1.0 a output leakage current i lo v out = v ss to v dd , output disable -1.0 +1.0 a output high voltage level v oh v dd = v dd (min), i oh = ?0.5ma 1.4 ? v output low voltage level v ol i ol = 1ma ? 0.4 v v dd power down current i ddps v dd = v dd max., v in = v ih or v il , ce2 0.2v ?10 a v dd standby current i dds v dd = v dd max., v in = v ih or v il ce 1 = ce2 = v ih ?1ma i dds1 v dd = v dd max., v in 0.2v or v in v dd ? 0.2v, ce 1 = ce2 v dd ? 0.2v ? 100 a v dd active current i dda1 v dd = v dd max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma t rc / t wc = minimum ?20ma i dda2 t rc / t wc = 1 s ?3ma
6 (ae3.0e) mb82ds01181e -70l-a ac characteristics (under recommended operating conditions unless otherwise noted) read operation notes *1: maximum value is applicable if ce 1 is kept at low without any address change. if the relaxation is needed by system operation, please contact local fujits u representative for the relaxation of 1 s limitation. *2: address should not be changed within minimum t rc . *3: the output load 50pf with 50ohm termination to v dd *0.5 v. *4: the output load 5pf without any other load. *5: applicable when ce 1 is kept at low. *6: t rc (min) must be satisfied. *7: if actual value of t whol is shorter than specified minimum values, the actual t aa of following read may become longer by the amount of subtracting actual value from specified minimum value. parameter symbol value unit notes min. max. read cycle time t rc 80 1000 ns *1, *2 ce 1 access time t ce ?70ns *3 oe access time t oe ?45ns *3 address access time t aa ?70ns*3, *5 lb / ub access time t ba ?30ns *3 output data hold time t oh 5?ns *3 ce 1 low to output low-z t clz 5?ns *4 oe low to output low-z t olz 0?ns *4 lb / ub low to output low-z t blz 0?ns *4 ce 1 high to output high-z t chz ?20ns *3 oe high to output high-z t ohz ?20ns *3 lb / ub high to output high-z t bhz ?20ns *3 address setup time to ce 1 low t asc ?5 ? ns address setup time to oe low t aso 10 ? ns address invalid time t ax ?10ns *5 address hold time from ce 1 high t chah ?5 ? ns *6 address hold time from oe high t ohah ?5 ? ns we high to oe low time for read t whol 15 1000 ns *7 ce 1 high pulse width t cp 15 ? ns
7 (ae3.0e) mb82ds01181e -70l-a ac characteristics (continued) write operation notes *1: maximum value is applicable if ce 1 is kept at low without any address change. if the relaxation is needed by system operation, please contact local fujits u representative for the relaxation of 1 s limitation. *2: minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wrc , t wr or t br ). *3: write pulse is defined from high to low transition of ce 1, we , or lb / ub , whichever occurs last. *4: applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce 1 or we whichever occurs last. *5: applicable for byte mask only. byte mask hold time is defined from the low to high transition of ce 1 or we whichever occurs first. *6: write recovery is defined from low to high transition of ce 1, we , or lb / ub , whichever occurs first. *7: if oe is low after minimum t ohcl , read cycle is initiated. in other word, oe must be brought to high within 5ns after ce 1 is brought to low. once r ead cycle is initiated, new write pulse should be input after minimum t rc is met. *8: if oe is low after new address input, read cycle is initiated. in other word, oe must be brought to high at the same time or before new address valid. once read cycle is initiated, new write pulse should be input after minimum t rc is met. parameter symbol value unit notes min. max. write cycle time t wc 80 1000 ns *1, *2 address setup time t as 0?ns *2 ce 1 write pulse width t cw 45 ? ns *3 we write pulse width t wp 45 ? ns *3 lb / ub write pulse width t bw 45 ? ns *3 lb / ub byte mask setup time t bs ?5 ? ns *4 lb / ub byte mask hold time t bh ?5 ? ns *5 write recovery time t wr 0?ns *6 ce 1 high pulse width t cp 15 ? ns we high pulse width t whp 15 1000 ns lb / ub high pulse width t bhp 15 1000 ns data setup time t ds 20 ? ns data hold time t dh 0?ns oe high to ce 1 low setup time for write t ohcl ?5 ? ns *7 oe high to address setup time for write t oes 0?ns *8 lb and ub write pulse overlap t bwo 20 ? ns
8 (ae3.0e) mb82ds01181e -70l-a ac characteristics (continued) power down parameters notes *1: applicable also to power-up. other timing parameters notes *1: some data might be written into any address location if t chwx (min) is not satisfied. *2: the input transition time (t t ) at ac testing is 5ns as shown in below. if actual t t is longer than 5ns, it may violate ac specification of some timing parameters. ac test conditions ac measurement output load circuit parameter symbol value unit note min. max. ce2 low setup time for power down entry t csp 10 ? ns ce2 low hold time after power down entry t c2lp 80 ? ns ce 1 high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? s*1 ce 1 high setup time following ce2 high after power down exit t chs 0?ns parameter symbol value unit note min. max. ce 1 high to oe invalid time for standby entry t chox 10 ? ns ce 1 high to we invalid time for standby entry t chwx 10 ? ns *1 ce 1 high hold time following ce2 high after power-up t chh 300 ? s input transition time t t 125ns*2 symbol description test setup value unit note v ih input high level v dd * 0.8 v v il input low level v dd * 0.2 v v ref input timing measurement level v dd * 0.5 v t t input transition time between v il and v ih 5ns device under test v dd v dd *0.5 v v ss out 0.1 f 50pf 50ohm
9 (ae3.0e) mb82ds01181e -70l-a timing diagrams read timing #1 (basic timing) see note. note: this timing diagram assumes ce2=h and we =h. read timing #2 (oe & address access) see note. notes: this timing diagram assumes ce2=h and we =h. t ce valid data output address ce 1 dq (output) oe t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz lb / ub t oe t ba t blz t clz t aa valid data output address ce 1 dq (output) lb / ub t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe t ax low t aa t ohah t aso
10 (ae3.0e) mb82ds01181e -70l-a timing diagrams (continued) read timing #3 (lb / ub byte access) see note. note: this timing diagram assumes ce2=h and we =h. t aa valid data output address ce 1, oe dq1-8 (output) ub t bhz t ba t rc t blz address valid valid data output t bhz t oh lb t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output
11 (ae3.0e) mb82ds01181e -70l-a timing diagrams (continued) write timing #1 (basic timing) see note. notes: this timing diagram assumes ce2=h. write timing #2 (we control) see note. note: this timing diagram assumes ce2=h. t as valid data input address ce 1 dq (input) we t dh t ds t wc t wr t wp t cw lb , ub t as t bw address valid t as t as t wr oe t ohcl t as t as t wr t cp t whp t bhp t as address we ce 1 t wc t wr t wp lb , ub address valid t as t wr t wp valid data input dq (input) t dh t ds oe t oes t ohz t wc valid data input t dh t ds low address valid t ohah t whp
12 (ae3.0e) mb82ds01181e -70l-a timing diagrams (continued) write timing #3-1 (we / lb / ub byte write control) see note. note: this timing diagram assumes ce2=h and oe =h. write timing #3-2 (we / lb / ub byte write control) see note. note: this timing diagram assumes ce2=h and oe =h. t as address we ce 1 t wc t wr t wp lb address valid t as t wr t wp valid data input dq1-8 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp t as address we ce 1 t wc t wr t bw lb address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp
13 (ae3.0e) mb82ds01181e -70l-a timing diagrams (continued) write timing #3-3 (we / lb / ub byte write control) see note. note: this timing diagram assumes ce2=h and oe =h. write timing #3-4 (we / lb / ub byte write control) see note. note: this timing diagram assumes ce2=h and oe =h. t as address we ce 1 t wc t wr t bw lb address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp t as address we ce 1 t wc t wr t bw lb address valid t as t wr t bw dq1-8 (input) t dh t ds ub t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t wr t bw t as t wr t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo t bhp t bhp
14 (ae3.0e) mb82ds01181e -70l-a timing diagrams (continued) read / write timing #1-1 (ce 1 control) see note. notes *1: this timing diagram assumes ce2=h. *2: write address is valid from either ce 1 or we of last falling edge. read / write timing #1-2 (ce 1 / we / oe control) see note. notes *1: this timing diagram assumes ce2=h. *2: oe can be fixed low during write operation if it is ce 1 controlled write at read-write-read se- quence. read data output address ce 1 dq we t wc t cw oe t ohcl ub , lb t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t clz t oh read data output address ce 1 dq we t wc t wp oe t ohcl ub , lb t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output
15 (ae3.0e) mb82ds01181e -70l-a timing diagrams (continued) read / write timing #2 (oe , we control) see note. notes *1: this timing diagram assumes ce2=h. *2: ce 1 can be tied to low for we and oe controlled operation. read / write timing #3 (oe , we , lb , ub control) see note. notes *1: this timing diagram assumes ce2=h. *2: ce 1 can be tied to low for we and oe controlled operation. read data output address ce 1 dq we t wc t wp oe ub , lb t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah t whol read data output address ce 1 dq we t wc t bw oe ub , lb t ba write address t as t rc write data input t ds t bhz t oh t aa read address t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes t whol t wr
16 (ae3.0e) mb82ds01181e -70l-a timing diagrams (continued) power-up timing see note. note: the t chh specifies after v dd reaches specified minimum level and applicable both ce1 and ce2. power down entry and exit timing see note. note: this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power-down program was not performed prior to this reset. standby entry timing after read or write see note. note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce 1 low to high transition. ce1 v dd v dd min 0v ce2 t chh t csp ce 1 power down entry ce2 t c2lp t chh power down mode power down exit t chs dq high-z t chox ce 1 oe we active (read) standby active (write) standby t chwx
17 (ae3.0e) mb82ds01181e -70l-a bonding pad bonding pad layout please contact local fujitsu representative for pad layout and pad coordinate information. bonding pad description pin name description a 19 to a 0 address input ce 1 chip enable (low active) ce2 chip enable (high active) we write enable (low active) oe output enable (low active) ub upper byte control (low active) lb lower byte control (low active) dq 16 - 9 upper byte data input/output dq 8 - 1 lower byte data input/output v dd power supply v ss ground test/open test/open (this pad should be left open. do not use.)
18 (ae3.0e) mb82ds01181e -70l-a fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3324 fax: +81-3-5322-3386 http://edevice.fujitsu.com/jp north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0409 ? 2003 - 2004 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third- party?s intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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